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products and specifications discussed herein ar e subject to change by micron without notice. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory features pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_1.fm - rev. f 12/ 06 en 1 ?2005 micron technology, inc. all rights reserved. async/page/burst cellularram? memory mt45w1mw16bdgb for the latest data sheet, refer to micron?s web site: www.micron.com/produ cts/psram/cellularram/ features ? single device supports asynchronous, page, and burst operations ? random access time: 70ns ?v cc , v cc q voltages: ? 1.7?1.95v v cc ? 1.7?3.3v v cc q ? page mode read access ? sixteen-word page size ? interpage read access: 70ns ? intrapage read access: 20ns ?burst mode write acce ss: continuous burst ? burst mode read access: ? 4, 8, or 16 words, or continuous burst ? max clock rate: 104 mhz ( t clk = 9.62ns) ? burst initial latency: 39 ns (4 clocks) @ 104 mhz ? t aclk: 7ns @ 104 mhz ?low power consumption ? asynchronous read: <20ma ? intrapage read: <15ma ? intrapage read initial access, burst read: ? (39ns [4 clocks] @ 104 mhz) < 35ma ? continuous burst read: <28ma ? standby: 70a ? deep power-down: <10a (typ @ 25c) ?low-power features ? temperature-compensated refresh (tcr) ? on-chip temperature sensor ? partial-array refresh (par) ? deep power-down (dpd) mode options designator ?configuration ? 1 meg x 16 mt45w1mw16bd ?package ? 54-ball vfbga (?green?) gb ?access time ? 70ns access -70 ?frequency ? 80 mhz 8 ? 104 mhz 1 figure 1: 54-ball vfbga notes: 1. ?30c exceeds the cellularram workgroup 1.0 specification of ?25c. 2. contact factory. part number example: mt45w1mw16bdgb-701wt options (continued) designator ?standby power ? standard none ? operating temperature range ? wireless (?30c to +85c) wt 1 ? industrial (?40c to +85c) it 2 a b c d e f g h j 1 2 3 4 5 6 top view (ball down) lb# dq8 dq9 v ss q v cc q dq14 dq15 a18 wait oe# ub# dq10 dq11 dq12 dq13 a19 a8 clk a0 a3 a5 a17 nc a14 a12 a9 adv# a2 ce# dq1 dq3 dq4 dq5 we# a11 nc cre dq0 dq2 v cc v ss dq6 dq7 nc nc a1 a4 a6 a7 a16 a15 a13 a10 nc
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23ztoc.fm - rev. f 12/ 06 en 2 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 functional block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 part numbering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 valid part number combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 power-up initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 bus operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 page mode read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 burst mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 mixed-mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 wait operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 lb#/ub# operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 low-power operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 standby mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 temperature-compensated refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 partial-array refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 deep power-down operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 access using cre . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 software access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 bus configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 burst length (bcr[2:0]) default = continuous burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 burst wrap (bcr[3]) default = burst no wrap (wi thin burst length) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 4 output impedance (bcr[5]) defaul t = outputs use full drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 wait configuration (bcr[8]) default = wait transitions on e clock before data valid/invalid . . . . . . . . .25 wait polarity (bcr[10]) default = wait active high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 latency counter (bcr[13:11]) default = three-clock latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 operating mode (bcr[15]) default = asynchronous operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 refresh configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 partial-array refresh (rcr[2:0]) default = full array refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 deep power-down (rcr[4]) default = dpd disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 temperature-compensated refresh (rcr[ 6:5]) default = on-chip temperature sensor. . . . . . . . . . . . . . . .28 page mode operation (rcr[7]) default = disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 maximum and typical standby currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 timing requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23zlof.fm - rev. f 12/ 06 en 3 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory list of figures list of figures figure 1: 54-ball vfbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: functional block diagram ? 1 meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 3: part number chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 4: power-up initialization timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 5: read operation (adv = low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 6: write operation (adv = low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 7: page mode read operation (adv = low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 8: burst mode read (4-wor d burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 9: burst mode write (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 10: wired-or wait configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 11: refresh collision during read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 12: refresh collision during write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 13: configuration register write in asynchronous mode followed by read array operation . . . .19 figure 14: configuration register write in synchronous mode followed by read array operation . . . . .20 figure 15: load configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 16: read configuration regi ster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 17: bus configuration register defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 18: wait configuration (bcr[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 19: wait configuration (bcr[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 20: wait configuration during burst operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 21: latency counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 22: refresh configuration register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 23: typical refresh current vs. temperature (i tcr ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 24: ac input/output reference wavefo rm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 25: output load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 26: initialization period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 27: asynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 28: asynchronous read using adv# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 29: page mode read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 30: single-access burst read operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 31: 4-word burst read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 32: read burst suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 33: continuous burst read showing an output de lay with bcr[8] = 0 for end-of-row condition . .43 figure 34: ce#-controlled asynchronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 35: lb#/ub#-controlled asyn chronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 36: we#-controlled asynchronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 37: asynchronous write using adv# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 38: burst write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 39: continuous burst write show ing an output delay with bcr[8] = 0 for end-of-row condition .49 figure 40: burst write followed by burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 41: asynchronous write followed by burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 42: asynchronous write followed by burst read ? adv# low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 43: burst read followed by asynchro nous write (we#-controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 44: burst read followed by asynchro nous write using adv# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 45: asynchronous write followed by asynchronous read ? adv# low . . . . . . . . . . . . . . . . . . . . . . . .55 figure 46: asynchronous write followed by asynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 47: 54-ball vfbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23zlot.fm - rev. f 12/ 06 en 4 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory list of tables list of tables table 1: vfbga ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 2: bus operations ? asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 3: bus operations ? burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 4: sequence and burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 5: latency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 6: 16mb address patterns for par (rcr[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 7: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 8: electrical characteristics and oper ating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 9: maximum standby currents for applying par and tcr settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 10: deep power-down specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 11: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 12: asynchronous read cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 13: burst read cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 14: asynchronous write cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 15: burst write cycle timing requiremen ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 16: initialization timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 5 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory general description general description micron ? cellularram? is a high-speed, cmos psram memory developed for low- power, portable applications. the mt45w1mw16bdgb is a 16mb dram core device organized as 1 meg x 16 bits. this device includes an industry-standard burst mode flash interface that dramatically increases read/write bandwidth compared with other low-power sram or pseudo sram offerings. for seamless operation on a burst flash bus, cellularram products incorporate a trans- parent self-refresh mechanism. the hidden re fresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. two user-accessible control registers define device operation. the bus configuration register (bcr) defines how the cellularram device interacts with the system memory bus and is nearly identical to its counterpar t on burst mode flash devices. the refresh configuration register (rcr) is used to co ntrol how refresh is performed on the dram array. these registers are automatically load ed with default settings during power-up and can be updated anytime during normal operation. special attention has been focused on standby current consumption during self refresh. cellularram products include three system-accessible mechanisms to minimize standby current. partial-array refresh (par) limits refresh to only that part of the dram array that contains essential data. temperat ure-compensated refresh (tcr) uses an on- chip sensor to adjust the refresh rate to ma tch the device temperature. the refresh rate decreases at lower temperatures to minimize current consumption during standby. tcr can also be set by the system for maximum device temperatures of +85c, +45c, and +15c. deep power-down (dpd) halts the refresh operation altogether and is used when no vital information is stored in the device. these three refresh mechanisms are accessed through the rcr.
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 6 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory functional block diagrams functional block diagrams figure 2: functional block diagram ? 1 meg x 16 note: functional block di agrams illustrate simplified device operation. see truth table, ball descriptions, and timing diagrams for detailed information. a[19:0] input/ output mux and buffers control logic 1,024k x 16 dram memory array ce# we# oe# clk adv# cre wait lb# ub# dq[7:0] dq[15:8] refresh configuration register (rcr) bus configuration register (bcr) address decode logic
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 7 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory ball descriptions ball descriptions note: the clk and adv# inputs can be tied to v ss if the device is always operating in asynchro- nous or page mode. wait will be asserted but should be ignored during asynchronous and page mode operations. table 1: vfbga ball descriptions vfbga assignment symbol type description g2, h1, d3, e4, f4, f3, g4, g3, h5, h4, h3, h2, d4, c4, c3, b4, b3, a5, a4, a3 a[19:0] input address inputs: inputs for addresses during read and write operations. addresses are internally la tched during read and write cycles. the address lines are also used to define the value to be loaded into the bus configuration register or the refresh conf iguration register. j2 clk input clock: synchronizes the memory to the system operating frequency during synchronous operations. when configured for synchronous operation, the address is latched on the first rising clk edge when adv# is active. clk is static low or high during asynchronous access read and write operations and during page read access operations. j3 adv# input address valid: indicates that a valid addr ess is present on the address inputs. addresses can be latched on the rising edge of adv# during asynchronous read and write operations. adv# can be held low during asynchronous read and write operations. a6 cre input configuration register enable: when cre is high, write operations load the refresh configuration register or bus configuration register. b5 ce# input chip enable: activate s the device when low. when ce# is high, the device is disabled and goes into standby or deep power-down mode. a2 oe# input output enable: enables the output buff ers when low. when oe# is high, the output buffers are disabled. g5 we# input write enable: determines if a given cycle is a write cycle. if we# is low, the cycle is a write to either a configuration register or to the memory array. a1 lb# input lower byte enable: dq[7:0]. b2 ub# input upper byte enab le: dq[15:8]. g1, f1, f2, e2, d2, c2, c1, b1, g6, f6, f5, e5, d5, c6, c5, b6 dq[15:0] input/ output data inputs/outputs. j1 wait output wait: provides data-valid feedback duri ng burst read and write operations. the signal is gated by ce#. wait is used to arbitrate collisions between refresh and read/write operations. wait is asserted when a burst crosses a row boundary. wait is also used to mask the delay asso ciated with opening a new internal page. wait is asserted and should be ignored during asynchronous and page mode operations. wait is hi gh-z when ce# is high. e3, h6, j4, j5, j6 nc ? not internally connected. d6 v cc supply device power supply (1.7?1 .95v): power supply for device core operation. e1 v cc q supply i/o power supply (1.7?3.3v): power supply for input/ output buffers. e6 v ss supply v ss must be connected to ground. d1 v ss q supply v ss q must be connected to ground.
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 8 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory bus operations bus operations notes: 1. clk must be low during as ync read and async write modes, and to achieve standby power during standby and dpd modes. clk must be static (high or low) during burst suspend. 2. the wait polarity is configured throug h the bus configuration register (bcr[10]). 3. when lb# and ub# are in select mode (low), dq[15:0] are af fected. when only lb# is in select mode, dq[7:0] ar e affected. when only ub# is in the select mode, dq[15:8] are affected. 4. the device will consume active power in this mode whenever addresses are changed. 5. when the device is in standby mode, addres s inputs and data inputs /outputs are internally isolated from any external influence. 6. v in = v cc q or 0v; all device balls must be static (unswitched) in order to achieve standby current. 7. dpd is maintained until rcr is reconfigured. 8. burst mode operation is initialized through the bus configuration register (bcr[15]). table 2: bus operations ? asynchronous mode mode power clk 1 adv# ce# oe# we# cre lb#/ ub# wait 2 dq[15:0] 3 notes read active l l l l h l l low-z data-out 4 write active l l l x l l l low-z data-in 4 standby standby l x h x x l x high-z high-z 5, 6 no operation idle l x l x x l x low-z x 4, 6 configuration register active l l lhlhxlow-zhigh-z dpd deep power-down l x h x x x x high-z high-z 7 table 3: bus operations ? burst mode mode power clk 1 adv# ce# oe# we# cre lb#/ ub# wait 2 dq[15:0] 3 notes async read active l l l l h l l low-z data-out 4 async write active l l l x l l l low-z data-in 4 standby standby l x h x x l x high-z high-z 5, 6 no operation idle l x l x x l x low-z x 4, 6 initial burst read active l l x h l l low-z x 4, 8 initial burst write active l l h l l x low-z x 4, 8 burst continue active h l x x x l low-z data-in or data-out 4, 8 burst suspend active x x l h x l x low-z high-z 4, 8 configuration register active l l h l h x low-z high-z 8 dpd deep power-down lxhxxxxhigh-zhigh-z7
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 9 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory part numbering information part numbering information micron cellularram devices ar e available in several differe nt configurations and densi- ties (see figure 3). figure 3: part number chart notes: 1. ?30c exceeds the cellularram workgroup 1.0 specification of ?25c. valid part number combinations after building the part number from the part numbering chart above, visit to the micron part marking decoder web site at www.micron.com/partsearch to verify that the part number is offered and valid. if the device requ ired is not on this list, contact the factory. device marking due to the size of the package, the micron standard part number is not printed on the top of the device. instead, an abbreviated de vice mark comprised of a five-digit alpha- numeric code is used. the abbreviated device marks are cross-referenced to the micron part numbers at www.micron.com/partsearch . to view the location of the abbreviated mark on the device, refer to customer serv ice note, csn-11, ?product mark/label? at www.micron.com/csn . mt 45 w 1m w 16 bd gb -70 8 wt es micron technology product family 45 = psram/cellularram memory operating core voltage w = 1.7?1.95v address locations m = megabits operating voltage w = 1.7?3.3v bus configuration 16 = x16 read/write operation mode bd = asynchronous/page/burst package codes gb = vfbga ?green? (6 x 9 grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm) 54-ball production status blank = production es = engineering sample ms = mechanical sample operating temperature wt = ?30c to +85c (see note 1) it = ?40c to +85c (contact factory) standby power options blank = standard frequency 8 = 80 mhz 1 = 104 mhz access/cycle time 70 = 70ns
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 10 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory functional description functional description in general, the mt45w1mw16bdgb devices ar e high-density alternatives to sram and pseudo sram products, popular in low-power, portable applications. the mt45w1mw16bdgb contains a 16,777,216-bit dram core organized as 1,048,576 addresses by 16 bits. this device implements the same high-speed bus interface found on burst mode flash products. the cellularram bus interface supports both asynchronous and burst mode transfers. page mode accesses are also included as a bandwidth-enhancing extension to the asyn- chronous read protocol. power-up initialization cellularram products include an on-chip volt age sensor used to launch the power-up initialization process. initialization will configure the bcr and the rcr with their default settings (s ee figure 17 on page 23 and figure 22 on page 27). v cc and v cc q must be applied simultaneously. when they reach a stable level at or above 1.7v, the device will require 150s to complete its self-initialization process. during the initialization period, ce# should remain high. when initiali zation is complete, the device is ready for normal operation. figure 4: power-up initialization timing bus operating modes the mt45w1mw16bdgb cellular ram products incorporate a burst mode interface found on flash products targeting low-power, wireless applications. this bus interface supports asynchronous, page mode, and burst mode read and write transfers. the specific interface supported is defined by the value loaded into the bus configuration register. page mode is controlled by th e refresh configuration register (rcr[7]). asynchronous mode cellularram products power up in the asyn chronous operating mode. this mode uses the industry-standard sram control bus (c e#, oe#, we#, lb#/ub#). read operations (figure 5) are initiated by bringing ce#, oe#, and lb#/ub# low while keeping we# high. valid data will be driven out of th e i/os after the specified access time has elapsed. write operations (figure 6 on page 11) occur when ce#, we#, and lb#/ub# are driven low. during asynchronous writ e operations, the oe# level is a ?don't care,? and we# will override oe#. the data to be written is latched on the rising edge of ce#, we#, or lb#/ub# (whichev er occurs first). asynchronous operations (page mode disabled) can either use the adv input to latch the address, or adv can be driven low during the entire read/write operation. during asynchronous operation, the clk input must be held static low or high. wait will be driven while the device is enabled and its state should be ignored. we# low time must be limited to t cem. v cc v cc q devi c e initialization v cc = 1.7v devi c e rea d y for normal operation t pu > 150s
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 11 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory bus operating modes figure 5: read operation (adv = low) note: adv must remain low for page mode operation. figure 6: write operation (adv = low) page mode read operation page mode is a performance-enhancing exte nsion to the legacy asynchronous read operation. in page-mode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be read quickly by simply changing the low- order address. addresses a[3:0] are used to determine the members of the 16-address cellularram page. any change in addresse s a[4] or higher will initiate a new t aa access time. figure 7 shows the timing for a page mo de access. page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. write operations do not incl ude comparable page mode functionality. during asynchronous page mode operation, the clk input must be held static low or high. ce# must be driven high upon completi on of a page mode access. wait will be driven while the device is enabled and its stat e should be ignored. page mode is enabled by setting rcr[7] to high. adv must be driven low during all page mode read accesses. addre ss valid data c e# data valid oe# we# lb#/ub# t r c = read c y c le time addre ss addre ss valid data c e# don ? t c are data valid oe# we# lb#/ub# t w c = write c y c le time addre ss < t c em
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 12 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory bus operating modes the ce# low time is limited by refresh considerations. ce# must not stay low longer than t cem. figure 7: page mode re ad operation (adv = low) burst mode operation burst mode operations enable high-speed synchronous read and write operations. burst operations consist of a multi-clock sequence that must be performed in an ordered fashion. after ce# goes low, the address to access is latched on the next rising edge of clk that adv# is low. during this first clock rising edge, we# indicates whether the operation is going to be a read (we# = high, figure 8 on page 13) or write (we# = low, figure 9 on page 14). the size of a burst can be specified in the bcr as either fixed-length or continuous. fixed-length bursts consist of four, eight, or sixteen words. continuous bursts have the ability to start at a specified address and burst through the entire memory. the latency count stored in the bcr defines the number of clock cycles that elapse before the initial data value is transferred between th e processor and cellularram device. the wait output will be asserted as soon as ce# goes low and will be de-asserted to indicate when data is to be transferred into (or out of ) the memory. wait will again be asserted if the burst crosses the bounda ry between 128-word rows. once the cellu- larram device has restored the previous row?s data and accessed the next row, wait will be de-asserted and the burst can continue (see figure 33 on page 43). the processor can access other devices with out incurring the timing penalty of the initial latency for a new burst by suspending burst mode. bursts are suspended by stop- ping clk. clk can be stopped high or low. if another device will use the data bus while the burst is suspended, oe# should be taken high to disable the cellularram outputs; otherwise, oe# can remain low. note that the wait output will continue to be active, and as a result no other devices shou ld directly share the wait connection to the controller. to continue the burst sequence, oe# is taken low, then clk is restarted after valid data is available on the bus. data c e# don ? t c are oe# we# lb#/ub# addre ss addre ss [0] addre ss [1] addre ss [2] addre ss [3] d[1] d[2] d[3] t aa t apa < t c em t apa t apa d[0]
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 13 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory bus operating modes the ce# low time is limited by refresh considerations. ce# must not stay low longer than t cem unless row boundaries are crossed at least every t cem. if a burst suspension will cause ce# to remain low for longer than t cem, ce# should be taken high and the burst restarted with a new ce# low/adv# low cycle. figure 8: burst mode read (4-word burst) note: non-default bcr settings: latency code tw o (three clocks); wait active low; wait asserted during delay. a[19:0] d[0] adv# c e# oe# d[1] d[2] d[3] we# wait dq[15:0] lb#/ub# laten c y c o d e 2 (3 c lo c ks) c lk undefined don ? t c are read burst i d entifie d (we# = hi g h) addre ss valid
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 14 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory bus operating modes figure 9: burst mode write (4-word burst) note: non-default bcr settings: latency code tw o (three clocks); wait active low; wait asserted during delay. a[19:0] d[0] adv# c e# oe# d[1] d[2] d[3] we# wait dq[15:0] lb#/ub# addre ss valid laten c y c o d e 2 (3 c lo c ks) c lk don ? t c are write burst i d entifie d (we# = low)
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 15 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory bus operating modes mixed-mode operation the device can support a combination of synchronous read and asynchronous write operations when the bcr is configured fo r synchronous operation. the asynchronous write operation requires that the clock (clk) be held static low or high during the entire sequence. the adv# signal can be used to latch the target address, or it can remain low during the entire write operation. ce# must return high when transi- tioning between mixed-mode operations. note that the t cka period is the same as a read or write cycle. this time is required to ensure adequate refresh. mixed-mode operation facilitates a seamless interface to legacy burst mode flash memory control- lers. see figure 41 on page 51. wait operation the wait output on a cellularram device is typically connected to a shared, system- level wait signal (see figure 10). the shared wait signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus. figure 10: wired-or wait configuration once a read or write operation has been initiated, wait goes active to indicate that the cellularram device requires additional time before data can be transferred. for read operations, wait will remain active until valid data is output from the device. for write operations, wait will indicate to th e memory controller when data will be accepted into the cellularram device. when wa it transitions to an inactive state, the data burst will progress on successive clock edges. during a burst cycle, ce# must remain asserted until the first data is valid. bringing ce# high during this initial latency may cause data corruption. the wait output also performs an arbitratio n role when a read or write operation is launched while an on-chip refresh is in progress. if a collision occurs, wait is asserted for additional clock cycles until the refresh has completed (see figures 11 and 12 on page 17). when the refresh operation has completed, the read or write operation will continue normally. wait is also asserted when a continuous read or write burst crosses a row boundary. the wait assertion allows time for the new row to be accessed and permits any pending refresh operations to be performed. lb#/ub# operation the lb# enable and ub# enable signals suppor t byte-wide data transfers. during read operations, the enabled byte(s) are driven onto the dqs. the dqs associated with a disabled byte are put into a high-z state du ring a read operation. during write oper- c ellularram external pull-up/ pull-down resistor pro c essor ready other devi c e wait other devi c e wait wait
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 16 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory bus operating modes ations, any disabled bytes will not be transf erred to the ram array and the internal value will remain unchanged. during an asynchronous write cycle, the data to be written is latched on the rising edge of ce#, we#, lb#, or ub#, whichever occurs first. when both the lb# and ub# are disabled (hig h) during an operation, the device will disable the data bus from receiving or transm itting data. although the device will seem to be deselected, it remains in an ac tive mode as long as ce# remains low. figure 11: refresh collision during read operation note: non-default bcr settings: latency code tw o (three clocks); wait active low; wait asserted during delay. a[19:0] adv# c e# oe# we# wait dq[15:0] c lk v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol d[2] d[1] d[3] valid addre ss a dd itional wait states inserte d to allow refresh c ompletion. lb#/ub# undefined don ? t c are d[0] hi g h-z
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 17 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory bus operating modes figure 12: refresh collision during write operation note: non-default bcr settings: latency code tw o (three clocks); wait active low; wait asserted during delay. a[19:0] adv# c e# oe# we# wait dq[15:0] c lk d[1] d[0] d[3] d[2] valid addre ss a dd itional wait states inserte d to allow refresh c ompletion. lb#/ub# don ? t c are v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol hi g h-z
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 18 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory low-power operation low-power operation standby mode operation during standby, the device current consumption is reduced to the level necessary to perform the dram refresh operation. stan dby operation occurs when ce# is high. the device will enter a reduced power state upon completion of a read or write oper- ation or when the address and control inputs remain static for an extended period of time. this mode will continue until a change occurs to the address or control inputs. temperature-compensated refresh temperature-compensated refresh (tcr) allo ws for adequate re fresh at different temperatures. this cellularram device includes an on-chip temperature sensor. when the sensor is enabled, it continually adjust s the refresh rate according to the operating temperature. the on-chip sens or is enabled by default. three fixed refresh rates are also available, corresponding to temperature thresholds of +15c, +45c, and +85c. the setting selected must be for a temperature higher than the case temperature of the cellularram device. if the case temperature is +35c, the system can minimize self refresh current consumption by selecting the +45c setting. the +15c setting would result in inadequate re freshing and cause data corruption. partial-array refresh partial-array refresh (par) restricts refresh operation to a portion of the total memory array. this feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. the refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. the mapping of these partitions can start at either the beginning or the end of the address map (see table 6 on page 28). read and write operations to address ranges receiving refresh will not be affected. data stored in addresses not receiving refresh will become corrupted. when re-enabling additional port ions of the array, the new portions are available immediately upon writing to the rcr. deep power-down operation deep power-down (dpd) operation disables all refresh-related activity. this mode is used if the system does not require the storage provided by the cellularram device. any stored data will become corrupted when dpd is enabled. when refresh activity has been re-enabled by rewriting the rcr, the cellula rram device will require 150s to perform an initialization procedure before normal operations can resume. during this 150s period, the current consumption will be high er than the specified standby levels, but considerably lower than the active current specification. dpd cannot be enabled or disabled by writing to the rcr using the software access sequence; the rcr should be accessed using cre instead.
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 19 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory configuration registers configuration registers two user-accessible configuration registers de fine the device operation. the bus config- uration register (bcr) defines how the cellul arram interacts with the system memory bus and is nearly identical to it s counterpart on burst mode fl ash devices. the refresh configu- ration register (rcr) is used to control how refresh is performed on the dram array. these registers are automatically loaded with default settings during power-up and can be updated any time the devices are operating in a standby state. access using cre the configuration registers are loaded using either a synchronous or an asynchronous write operation when the configuration re gister enable (cre) input is high (see figure 13 on page 19 and figure 14 on page 20). when cre is low, a read or write operation will access the memory array. the register values are placed on address pins a[19:0]. in an asynchronous write, the values are latched into the configuration register on the rising edge of adv#, ce#, or we#, whichever occurs first; lb# and ub# are ?don?t care.? access using cre is write only. the bcr is accessed when a[19] is high; the rcr is accessed when a[19] is low. figure 13: configuration register write in asynchronous mode foll owed by read array operation note: a[19] = low to load rcr ; a[19] = high to load bcr. a[18:0] c lk op c ode addre ss addre ss data valid a19 1 adv# c e# oe# we# lb#/ub# dq[15:0] initiate c ontrol re g ister a cc ess write a dd ress bus value to c ontrol re g ister c re t av s t avh t avh t av s t vp t vph t c ph t wp t c w don ? t c are s ele c t c ontrol re g ister
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 20 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory configuration registers figure 14: configuration register write in synchronous mode followed by read array operation notes: 1. non-default bcr settings for cr write in synchronous mode followed by read array operation: latency code two (thr ee clocks); wait active low; wait asserted during delay. 2. a[19] = low to load rcr; a[19] = high to load bcr. 3. ce# must remain low to complete a burst-of -one write. wait must be monitored?addi- tional wait cycles caused by refresh collis ions require a corresponding number of addi- tional ce# low cycles. c lk a[18:0] a19 2 c re adv# c e# oe# we# lb#/ub# wait dq[15:0] t s p t s p t s p t hd t hd t hd t cs p t s p t hd hi g h-z op c ode addre ss hi g h-z t c ew lat c h c ontrol re g ister value lat c h c ontrol re g ister a dd ress t c bph 3 data valid addre ss don ? t c are
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 21 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory configuration registers software access software access of the configuration registers uses a sequence of asynchronous read and asynchronous write operations. the conten ts of the configuration registers can be read or modified using the software sequence. the configuration registers are loaded using a four-step sequence consisting of two asynchronous read operations followed by two asynchronous write operations (see figure 15). the read sequence is virtually iden tical except that an asynchronous read is performed during the fourth operation (see fi gure 16). note that a third read cycle of the highest address will cancel the access sequence until a different address is read. the address used during all read and write operations is the highest address of the cellularram device being accessed (fffffh for 16mb); the content at this address is not changed by using this sequence. the data value presented during the third operation (write) in the sequence defines whether the bcr or the rcr is to be accessed . if the data is 0000h, the sequence will access the rcr; if the data is 0001h, the se quence will access the bcr. during the fourth operation, dq[15:0] transfer data into or out of bits 15?0 of the configuration registers. the use of the software sequence does not affect the ability to perform the standard (cre-controlled) method of loading the conf iguration registers. however, the software nature of this access mechanism eliminates the need for the control register enable (cre) pin. if the software mechanism is used, the cre pin can simply be tied to v ss . the port line often used fo r cre control purposes is no longer required. software access of the rcr should not be used to enter or exit dpd. figure 15: load configuration register addre ss (max) addre ss (max) addre ss (max) xxxxh xxxxh r c r: 0000h b c r: 0001h c r value in addre ss c e# oe# we# lb#/ub# data don't c are read read write write addre ss (max)
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 22 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory configuration registers figure 16: read configuration register addre ss (max) addre ss (max) addre ss (max) xxxxh xxxxh c r value out addre ss c e# oe# we# lb#/ub# data don't c are read read write read r c r: 0000h b c r: 0001h addre ss (max)
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 23 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory configuration registers bus configuration register the bcr defines how the cellularram device interacts with the system memory bus. page mode operation is enabled by a bit contained in the rcr. figure 17 describes the control bits in the bcr. at power-up, the bcr is set to 9d4fh. the bcr is accessed using cre and a[19] high or through the configuration register software sequence with dq = 0001h on the third cycle. figure 17: bus configuration register definition note: all burst writes are continuous. a13 13 12 11 0 laten c y c ounter 3 21 wait polarity 4 5 wait c onfi g uration (w c ) c lo c k c onfi g uration ( cc ) 6 7 8 output impe d an c e burst wrap (bw)* 14 a12a11 a10 a9 a8 a7 a 6 a5 a4 a3 a2 a1 a0 0 1 operation mode s yn c hronous b urst a cc ess mo d e asyn c hronous a cc ess mo d e ( d efault) bcr[12] bcr[11] latency counter bcr[13] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 c o d e 0?reserve d c o d e 1?reserve d c o d e 2 c o d e 3 (default) c o d e 4?reserve d c o d e 5?reserve d c o d e 6 ?reserve d c o d e 7?reserve d 0 1 wait polarity a c tive low a c tive hi g h ( d efault) bcr[10] 0 1 wait configuration asserte d d urin g d elay asserte d one d ata c y c le b efore d elay ( d efault) 0 1 output impedance full drive ( d efault) 1/4 drive bcr[5] burst wrap (note 1) burst wraps within the b urst len g th burst no wrap ( d efault) bcr[3] bcr[1] bcr[0] burst length (note 1) bcr[2] 15 burst len g th (bl)* reserve d reserve d 9 10 reserve d operatin g mo d e reserve d a14 a15 a[18:1 6 ] 0 1 register select s ele c t r c r s ele c t b c r must b e set to "0" 19 18?1 6 re g ister s ele c t a19 reserve d must b e set to "0" must b e set to "0" must b e set to "0" must b e set to "0" bcr[8] 0 1 clock configuration not supporte d risin g e dg e ( d efault) bcr[6] bcr[15] bcr[19] 0 1 0 0 0 1 0 1 1 1 1 0 1 1 4 wor d s 8 wor d s 1 6 wor d s c ontinuous b urst ( d efault)
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 24 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory configuration registers burst length (bcr[2:0]) default = continuous burst burst lengths define the number of words th e device outputs during a burst read oper- ation. the device supports a burst length of 4, 8, or 16 words. the device can also be set in continuous burst mode where data is output sequentially without regard to address boundaries; the internal address wraps to 000000h if the device is read past the last address. write bursts are always pe rformed using continuous burst mode. burst wrap (bcr[3]) default = burst no wrap (within burst length) the burst wrap option determines if a 4-, 8-, or 16-word burst read wraps within the burst length or steps through sequential addres ses. if the wrap option is not enabled, the device outputs data from sequential addres ses without regard to burst boundaries; the internal address wraps to 000000h if the device is read past the last address. table 4: sequence and burst length burst wrap starting address 4-word burst length 8-word burst length 16-word burst length continuous burst bcr[3] wrap (decimal) linear linear linear linear 0yes 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 -8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-? 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8 -9-10-11-12-13-14-15-0 1-2-3-4-5-6-7-? 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9 -10-11-12-13-14-15-0-1 2-3-4-5-6-7-8-? 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-1 0-11-12-13-14-15-0-1-2 3-4-5-6-7-8-9-? 4 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11- 12-13-14-15-0-1-2-3 4-5-6-7-8-9-10-? 5 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12- 13-14-15-0-1-2-3-4 5-6-7-8-9-10-11-? 6 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13 -14-15-0-1-2-3-4-5 6-7-8-9-10-11-12- 7 7-0-1-2-3-4-5-6 7-8-9-10 -11-12-13-14-15-0-1-2-3-4-5-6 7-8-9-10-11-12-13-? ... ... ... 14 14-15-0-1-2-3-4-5-6-7-8-9-10- 11-12-13 14-15-16-17-18-19-20- ... 15 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17-18-19-20- 21... 1no 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 -8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-? 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8 -9-10-11-12-13-14-15-16 1-2-3-4-5-6-7-? 2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16- 17 2-3-4-5-6-7-8-? 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5- 6-7-8-9-10-11-12-13-14-15-16-17- 18 3-4-5-6-7-8-9-? 4 4-5-6-7-8-9-10-11 4-5-6-7-8- 9-10-11-12-13-14-15-16-17- 18-19 4-5-6-7-8-9-10-? 5 5-6-7-8-9-10-11-12 5-6-7-8-9-10-11-12-13-...-15-16-17-18- 19-20 5-6-7-8-9-10-11? 6 6-7-8-9-10-11-12- 13 6-7-8-9-10-11-12-13-14-...-16-17-18-19- 20-21 6-7-8-9-10-11-12? 7 7-8-9-10-11-12-13- 14 7-8-9-10-11-12-13-14-...-17-18-19-20- 21-22 7-8-9-10-11-12-13? ... ... ... 14 14-15-16-17-18-19-...-23-24-25-26-27- 28-29 14-15-16-17-18-19-20- ? 15 15-16-17-18-19-20-...-24-25-26-27-28- 29-30 15-16-17-18-19-20-21- ?
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 25 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory configuration registers output impedance (bcr[ 5]) default = outputs use full drive strength the output driver strength can be altered to adjust for different data bus loading scenarios. the reduced-strength option should be more than adequate in stacked chip (flash + cellularram) environments when there is a dedicated memory bus. the reduced- drive-strength option is included to minimize noise generated on the data bus during read operations. normal output impedance sh ould be selected when using a discrete cellularram device in a more heavily loaded data bus environment. partial drive is approximately one-quarter full drive streng th. outputs are configured at full drive strength during testing. wait configuration (bcr[8]) default = wait tran sitions one clock before data valid/invalid the wait configuration bit is used to de termine when wait transitions between the asserted and the de-asserted state with respec t to valid data presented on the data bus. the memory controller will use the wait si gnal to coordinate data transfer during synchronous read and write operations. when bc r[8] = 0, data will be valid or invalid on the clock edge immediately after wait transitions to the de-asserted or asserted state, respectively (see figures 18 and 20). when bcr[8] = 1, the wait signal transitions one clock period prior to the data bus going valid or invalid (see figures 19 and 20). wait polarity (bcr[10]) default = wait active high the wait polarity bit indicates whether an asserted wait output should be high or low. this bit will determine whether the wait signal requires a pull-up or pull-down resistor to maintain the de-asserted state. figure 18: wait configuration (bcr[8] = 0) note: data valid/invalid immediat ely after wait transitions (bcr[8] = 0). see figure 20 on page 26. figure 19: wait configuration (bcr[8] = 1) note: valid/invalid data delayed for one clock after wait transitio ns (bcr[8] = 1). see figure 20 on page 26. wait dq[15:0] c lk data[0] data[1] data imme d iately vali d (or invali d ) hi g h-z wait d[15:0] c lk data[0] data vali d (or invali d ) after one c lo c k d elay hi g h-z
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 26 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory configuration registers figure 20: wait configuration during burst operation note: non-default bcr setting for wait du ring burst operation: wait active low. latency counter (bcr[13:11]) default = three-clock latency the latency counter bits determine how many clocks occur between the beginning of a read or write operation and the first data value transferred. only latency code two (three clocks) or latency code three (four cl ocks) is allowed (see table 5 and figure 21). operating mode (bcr[15]) default = asynchronous operation the operating mode bit selects either sy nchronous burst operation or the default asynchronous mode of operation. figure 21: latency counter table 5: latency configuration latency configuration code max input clk frequency (mhz) 104 mhz 80 mhz 2 (3 clocks) 66 (15ns) 53 (18.75ns) 3 (4 clocks) ? default 104 (9.62ns) 80 (12.50ns) wait wait dq[15:0] c lk d[0] d[1] b c r[8] = 0 data vali d in c urrent c y c le. b c r[8] = 1 data vali d in next c y c le. don ? t c are d[2] d[3] d[4] a[19:0] adv# dq[15:0] c lk c o d e 2 valid output valid output valid output valid output valid output valid output valid output valid output valid output c o d e 3 (default) dq[15:0] don ? t c are undefined v ih v il v ih v il v ih v il v oh v ol v oh v ol valid addre ss
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 27 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory configuration registers refresh configuration register the refresh configuration register (rcr) defines how the cellularram device performs its transparent self refresh. altering the refresh parameters can dramatically reduce current consumption during standby mode. page mode control is also embedded into the rcr. figure 22 describes the control bits used in the rcr. at power-up, the rcr is set to 0010h. the rcr is accessed using cre and a[19] lo w; or through the configuration register software access sequence with dq = 0000h on the third cycle (see ?configuration regis- ters? on page 19.) partial-array refresh (rcr[2:0] ) default = full array refresh the par bits restrict refresh operation to a portion of the total memory array. this feature allows the device to reduce standby cu rrent by refreshing only that part of the memory array required by the host system. the refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. the mapping of these partitions can start at either the beginning or the end of the address map (see table 6 on page 28). figure 22: refresh configuration register mapping par a4 a3 a2 a1 a0 a dd ress bus 4 5 1 2 3 0 re s erved re s erved 6 a5 0 1 deep power-down dpd ena b le dpd disa b le ( d efault) rcr[4] t c r rcr[6] rcr[5] 1 1 1 1 0 0 0 0 maximum case temp. +85 c internal sensor ( d efault) +45 c +15 c a 6 all must b e set to "0" a[18:8] 18?8 19 re g ister s ele c t a19 0 1 register select s ele c t r c r s ele c t b c r rcr[19] rcr[1] 0 0 1 1 rcr[0] 0 1 0 1 refresh coverage full array ( d efault) bottom 1/2 array bottom 1/4 array bottom 1/8 array rcr[2] 0 0 0 0 00 1 0 1 1 1 0 1 11 1 none of array top 1/2 array top 1/4 array top 1/8 array dpd must b e set to "0" a7 7 pa g e 0 1 page mode enable/disable pa g e mo d e disa b le d ( d efault) pa g e mo d e ena b le rcr[7]
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 28 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory configuration registers deep power-down (rcr[4]) default = dpd disabled the deep power-down bit enables and disables all refresh-related activity. this mode is used if the system does not require the storage provided by the cellularram device. any stored data will become corrupted when dpd is enabled. when refresh activity has been re-enabled, the cellularram device will require 150s to perform an initialization procedure before normal operations can resume. deep power-down is enabled when rcr[4] = 0, and remains enabled until rcr[4] is set to ?1.? dpd should not be enabled or disabled with the software access sequence; instead, use cre to access the rcr. temperature-compensated refresh (rcr[6:5 ]) default = on-chip temperature sensor this cellularram device includes an on-c hip temperature sensor that automatically adjusts the refresh rate according to the operating temperature. the on-chip tcr is enabled by clearing both of the tcr bits in the refresh configuration register (rcr[6:5] = 00b). any other tcr setting enables a fixed refresh rate. when the on-chip temperature sensor is enabled, the device continually adjusts the refresh rate according to the oper- ating temperature. the tcr bits also allow for ad equate fixed-rate refresh at three different temperature thresholds (+15c, +45c, and +85c). the se tting selected must be for a temperature higher than the case temperature of the ce llularram device. if the case temperature is +35c, the system can mi nimize self refresh current consumption by selecting the +45c setting. the +15c setting would resu lt in inadequate refreshing and cause data corruption. page mode operation (rcr[7]) default = disabled the page mode operation bit determines wh ether page mode is enabled for asynchro- nous read operations. in the power-up default state, page mode is disabled. table 6: 16mb address patterns for par (rcr[4] = 1) rcr[2] rcr[1] rcr[0] active section address space size density 0 0 0 full die 000000h?0fffffh 1 meg x 16 16mb 0 0 1 one-half of die 000000h?07ffffh 512k x 16 8mb 0 1 0 one-quarter of die 000000h?03ffffh 256k x 16 4mb 0 1 1 one-eighth of die 00 0000h?01ffffh 128k x 16 2mb 1 0 0 none of die 0 0 meg x 16 0mb 1 0 1 one-half of die 80000h?0fffffh 512k x 16 8mb 1 1 0 one-quarter of die c0000h?0fffffh 256k x 16 4mb 1 1 1 one-eighth of die e0000h?0fffffh 128k x 16 2mb
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 29 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory electrical characteristics electrical characteristics notes: 1. ?30c exceeds the cellularram workgroup 1.0 specification of ?25c. stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at thes e or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. table 7: absolute maximum ratings parameter rating voltage to any ball except v cc , v cc q relative to v ss ?0.5v to (4.0v or v cc q + 0.3v, whichever is less) voltage on v cc supply relative to v ss ?0.2v to +2.45v voltage on v cc q supply relative to v ss ?0.2v to +4.0v storage temperature (plastic) ?55oc to +150oc operating temperature (case) wireless 1 industrial ?30oc to +85oc ?40oc to +85oc soldering temper ature and time 10 seconds (solder ball only) +260oc
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 30 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory electrical characteristics notes: 1. ?30c exceeds the cellularram workgroup 1.0 specification of ?25c. 2. input signals may overshoot to v cc q + 1.0v for periods less than 2ns during transitions. 3. v ih (min) value is not aligned with cellularram work group 1.0 specification of v cc q - 0.4v. 4. input signals ma y undershoot to v ss - 1.0v for periods less than 2ns during transitions. 5. bcr[5] = 0b. 6. this parameter is specified with the outputs di sabled to avoid external loading effects. the user must add the current required to drive out put capacitance expected in the actual sys- tem. 7. i sb (max) values measured with par set to fu ll array and tcr set to +85c. in order to achieve low standby current, all in puts must be driven to either v cc q or v ss . i sb might be slightly higher fo r up to 500ms after power-up, after changes to the par array partition, or when entering standby mode. table 8: electrical characteristics and operating conditions wireless temperature 1 (?30oc < t c < +85oc); industrial te mperature (?40oc < t c < +85oc) description conditions symbol min max units notes supply voltage v cc 1.7 1.95 v i/o supply voltage v cc q1.73.3v input high voltage v ih 1.4 v cc q + 0.2 v 2, 3 input low voltage v il ?0.2 0.4 v 4 output high voltage i oh = ?0.2ma v oh 0.8 v cc qv5 output low voltage i ol = +0.2ma v ol 0.2 v cc qv 5 input leakage current v in = 0 to v cc qi li 1a output leakage current oe# = v ih or chip disabled i lo 1a operating current asynchronous random read/ write v in = v cc q or 0v chip enabled, i out = 0 i cc 1?70 20ma6 asynchronous page read i cc 1p ?70 15 ma 6 initial access, burst read/write i cc 2 104 mhz 35 ma 6 80 mhz 30 continuous burst read i cc 3r 104 mhz 28 ma 6 80 mhz 22 continuous burst write i cc 3w 104 mhz 33 ma 6 80 mhz 25 standby current v in = v cc q or 0v ce# = v cc q i sb standard 70 a 7
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 31 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory electrical characteristics maximum and typical standby currents the following table and figure refer to the maximum and typical standby currents for the mt45w1mw16bdgb device. the typical values shown in figure 23 are measured with the default on-chip temperature sensor control enabled. the maximum values shown in table 9 are measured with the relevant tcr bits set in the configuration register. notes: 1. for rcr[6:5] = 00b (default ) refer to figure 23, typical refresh current vs. temperature (itcr) for typical values. 2. in order to achieve low standby curr ent, all inputs must be driven to v cc q or v ss . i sb might be slightly higher for up to 500ms after power-up, after chan ges to the par array portion, or when entering standby mode. 3. tcr values for 85c are 100 percent tested. tcr values for 15c and 45c are sampled only. 4. typical i sb currents for each par setting with the appropriate tcr selected, or temperature sensor enabled. figure 23: typical refresh current vs. temperature (i tcr ) note: typical i sb currents for each par sett ing with the approp riate tcr selected, or temperature sensor enabled. table 9: maximum standby currents for applying par and tcr settings par tcr units +15c (rcr[6:5] = 10b) +45c (rcr[6:5] = 01b) +85c (rcr[6:5] = 11b) full array 45 60 70 a 1/2 array 40 55 65 a 1/4 array 37 50 60 a 1/8 array 37 50 60 a 0 array 35 45 55 a 0 5 10 15 20 25 30 35 40 45 50 -45 c -35 c -25 c -15 c -05 c 05 c 15 c 25 c 35 c 45 c 55 c 6 5 c 75 c 85 c temperature ( c ) i s b (a) par full par 1/2 par 1/4 par 0
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 32 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory electrical characteristics notes: 1. these parameters are verified in device characterization and are not 100-percent tested. figure 24: ac input/output reference waveform notes: 1. ac test inputs are driven at v cc q for a logic 1 and v ss q for a logic 0. input rise and fall times (10% to 90%) < 1.6ns. 2. input timing begins at v cc /2. due to the possibility of a difference between v cc and v cc q, the input test point may not be shown to scale. 3. output timing ends at v cc q/2. figure 25: output load circuit notes: 1. all tests are performed with the outputs co nfigured for full drive strength (bcr[5] = 0b). table 10: deep power-down specifications description conditions symbol typ units deep power-down v in = v cc q or 0v; +25c i zz 10 a table 11: capacitance description conditions symbol min max units notes input capacitance t c = +25oc; f = 1 mhz; v in = 0v c in 2.0 6.5 pf 1 input/output capacitance (dq) c io 3.0 6.5 pf 1 output test points input 1 v cc q v ss q v cc q/2 3 v cc /2 2 dut vccq/2 30pf test point 50
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 33 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing requirements timing requirements notes: 1. all tests are performed with the outputs co nfigured for full drive strength (bcr[5] = 0b). 2. low-z to high-z timings are tested with the circuit shown in figure 25 on page 32. the high-z timings measure a 100mv transition fr om either v oh or v ol toward v cc q/2. 3. high-z to low-z timi ngs are tested with the circuit shown in figure 25 on page 32. the low- z timings measure a 100mv trans ition away from the high-z (v cc q/2) level toward either v oh or v ol . 4. page mode en abled only. table 12: asynchronous read cycle timing requirements parameter 1 symbol 70ns units notes min max address access time t aa 70 ns adv# access time t aadv 70 ns page access time t apa 20 ns address hold from adv# high t avh 5 ns address setup to adv# high t avs 10 ns lb#/ub# access time t ba 70 ns lb#/ub# disable to dq high-z output t bhz 8 ns 4 lb#/ub# enable to low-z output t blz 10 ns 3 maximum ce# pulse width t cem 8 s 2 ce# low to wait valid t cew 1 7.5 ns chip select access time t co 70 ns ce# low to adv# high t cvs 10 ns chip disable to dq and wait high-z output t hz 8 ns 4 chip enable to low-z output t lz 10 ns 3 output enable to valid output t oe 20 ns output hold from address change t oh 5 ns output disable to dq high-z output t ohz 8 ns 4 output enable to low-z output t olz 3 ns 3 page cycle time t pc 20 ns read cycle time t rc 70 ns adv# pulse width low t vp 10 ns adv# pulse width high t vph 10 ns
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 34 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing requirements notes: 1. all tests are performed with the outputs co nfigured for full drive strength (bcr[5] = 0b). 2. when configured for synchronous mode (bcr [15] = 0), a refresh opportunity must be pro- vided every t cem. a refresh opportunity is satisfied by either of the following two condi- tions: a) clocked ce# high, or b) ce# high for greater than 15ns. 3. low-z to high-z timings are tested with the circuit shown in figure 25 on page 32. the high-z timings measure a 100mv transition fr om either v oh or v ol toward v cc q/2. 4. high-z to low-z timi ngs are tested with the circuit shown in figure 25 on page 32. the low- z timings measure a 100mv trans ition away from the high-z (v cc q/2) level toward either v oh or v ol . table 13: burst read cycle timing requirements parameter 1 symbol 104 mhz 80 mhz units notes min max min max burst to read access time t aba 35 46.5 ns clk to output delay t aclk 7 9 ns burst oe# low to output delay t boe 20 20 ns ce# high between subsequent burst and mixed-mode operations t cbph 5 5 ns 2 maximum ce# pulse width t cem 8 8 s ce# low to wait valid t cew 1 7.5 1 7.5 ns clk period t clk 9.62 20 12.5 20 ns ce# setup time to active clk edge t csp 3 20 4.5 20 ns hold time from active clk edge t hd 2 2 ns chip disable to dq and wait high-z output t hz 8 8 ns 3 clk rise or fall time t khkl 1.6 1.8 ns clk to wait valid t khtl 7 9 ns output hold from clk t koh 2 2 ns clk high or low time t kp 3 4 ns output disable to dq high-z output t ohz 8 8 ns 3 output enable to low-z output t olz 3 3 ns 4 setup time to active clk edge t sp 3 3 ns
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 35 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing requirements notes: 1. high-z to low-z timings are tested with th e circuit shown in figure 25 on page 32. the low- z timings measure a 100mv trans ition away from the high-z (v cc q/2) level toward either v oh or v ol . 2. low-z to high-z timings are tested with the circuit shown in figure 25 on page 32. the high-z timings measure a 100mv transition fr om either v oh or v ol toward v cc q/2. 3. we# low time must be limited to t cem (8s). table 14: asynchronous write cycle timing requirements parameter symbol 70ns units notes min max address and adv# low setup time t as 0 ns address hold from adv# going high t avh 5 ns address setup to adv# going high t avs 10 ns address valid to end of write t aw 70 ns lb#/ub# select to end of write t bw 70 ns ce# low to wait valid t cew 1 7.5 ns async address-to-burst transition time t cka 70 ns ce# high between subsequent asynchronous operations t cph 5 ns ce# low to adv# high t cvs 10 ns chip enable to end of write t cw 70 ns data hold from write time t dh 0 ns data write setup time t dw 23 ns chip disable to wait high-z output t hz 8 ns chip enable to low-z output t lz 10 ns 1 end write to low-z output t ow 5 ns 1 adv# pulse width t vp 10 ns adv# pulse width high t vph 10 ns adv# setup to end of write t vs 70 ns write cycle time t wc 70 ns write to dq high-z output t whz 8 ns 2 write pulse width t wp 46 ns 3 write pulse width high t wph 10 ns write recovery time t wr 0 ns
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 36 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing requirements notes: 1. when configured for synchronous mode (b cr[15] = 0), a refresh opportunity must be pro- vided every t cem. a refresh opportunity is satisfied by either of the following two condi- tions: a) clocked ce# high, or b) ce# high for greater than 15ns. figure 26: initialization period table 15: burst write cycle timing requirements parameter symbol 104 mhz 80 mhz units notes min max min max ce# high between subsequent burst and mixed-mode operations t cbph 5 5 ns 1 minimum ce# pulse width t cem 8 8 s 1 ce# low to wait valid t cew 1 7.5 1 7.5 ns clock period t clk 9.62 20 12.5 20 ns ce# setup to clk active edge t csp 3 20 4.5 20 ns hold time from active clk edge t hd 2 2 ns chip disable to wait high-z output t hz 8 8 ns clk rise or fall time t khkl 1.6 1.8 ns clock to wait valid t khtl 7 9 ns clk high or low time t kp 3 4 ns setup time to active clk edge t sp 3 3 ns table 16: initialization timing parameters parameter symbol -70 units min max initialization period (require d before normal operations) t pu 150 s t pu v cc , v cc q = 1.7v v cc (min) devi c e rea d y for normal operation
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 37 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing diagrams timing diagrams figure 27: asynchronous read v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol a[19:0] adv# c e# lb#/ub# oe# we# wait dq[15:0] valid addre ss t aa t hz t ba hi g h-z hi g h-z t r c t c o t bhz t ohz t oe t c ew t hz valid output hi g h-z undefined don ? t c are t blz t lz t olz
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 38 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 28: asynchro nous read using adv# a[19:0] adv# c e# lb#/ub# oe# we# wait dq[15:0] valid addre ss t vph t aadv t aa t vp t hz t ba hi g h-z hi g h-z t c v s t c o t blz t bhz t ohz t lz t oe t olz valid output t avh t av s hi g h-z undefined don ? t c are t c ew t hz v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 39 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 29: page mode read a[3:0] adv# c e# lb#/ub# oe# we# wait dq[15:0] valid addre ss t aa t hz t ba hi g h-z hi g h-z t c o t c em t blz t bhz t ohz t lz t oe t olz t c ew t hz hi g h-z undefined don ? t c are a[19:4] valid addre ss valid addre ss valid addre ss valid addre ss t r c valid output t apa t p c v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol t oh valid output valid output valid output
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 40 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 30: single-access burst read operation notes: 1. non-default bcr settings for single-acces s burst read operation: latency code two (three clocks); wait active low; wait asserted during delay. a[19:0] v ih v il adv# v ih v il c e# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol c lk v ih v il v oh v ol t s p t c lk t a c lk t c ew t hd t aba valid output valid addre ss hi g h-z t koh t ohz t s p t hd lb#/ub# v ih v il t cs p t c em hi g h-z t olz hi g h-z t hd t hz t kp t kp t khkl t hd t s p undefined don ? t c are read burst i d entifie d (we# = hi g h) t khtl t boe
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 41 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 31: 4-word burst read operation note: non-default bcr settings for 4-word burs t read operation: latency code two (three clocks); wait active low; wait asserted during delay. a[19:0] v ih v il adv# v ih v il c e# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol c lk v ih v il v oh v ol t s p t c lk t khkl t hd t aba valid addre ss hi g h-z t koh t hz t hd t s p t hd lb#/ub# v ih v il hi g h-z t olz t c bph t cs p t c em t s p t hd t ohz t kp t kp undefined don ? t c are read burst i d entifie d (we# = hi g h) t c ew t a c lk t khtl valid output valid output valid output valid output t boe hi g h-z
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 42 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 32: read burst suspend note: non-default bcr settings for read burst su spend: latency code two (three clocks); wait active low; wait asserted during delay. a[19:0] v ih v il adv# v ih v il c e# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol c lk v ih v il v oh v ol t s p t hd hi g h-z t olz t a c lk lb#/ub# v ih v il t c lk t s p t hd t cs p t c em t s p t hd t koh valid output valid output valid addre ss hi g h-z t c bph t hz t ohz valid output valid output valid output valid output t boe t ohz t boe t olz valid addre ss hi g h-z don ? t c are undefined
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 43 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 33: continuous burst read showing an output delay with bcr[8] = 0 for end-of-row condition notes: 1. non-default bcr settings for continuous burst read showing an output delay, bcr[8] = 0 for end-of-row condition: latency code two (three clocks); wait active low; wait asserted during delay. 2. wait will be asserted a maxi mum of (2 lc) cycles (bcr[8] = 0; wait asserted during delay). lc = latenc y code (b cr[13:11]). 3. ce# must not remain low longer than t cem. t a c lk t koh a[19:0] v ih v il adv# v ih v il c e# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol c lk v ih v il v oh v ol t khtl t khtl t c lk lb#/ub# v ih v il valid output valid output valid output valid output note 2 note 3 don ? t c are
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 44 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 34: ce#-controlled asynchronous write a[19:0] adv# c e# lb#/ub# oe# we# wait dq[15:0] in valid addre ss hi g h-z hi g h-z t w c t c ew t hz valid input t aw don ? t c are t wr t c w t dw dq[15:0] out t whz t bw t lz t dh t a s t wp t wph v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol hi g h-z t c ph
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 45 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 35: lb#/ub#-controlled asynchronous write v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[19:0] adv# c e# lb#/ub# oe# we# wait dq[15:0] in v ih v il valid addre ss hi g h-z t w c t c ew t hz valid input t aw don ? t c are t wr t c w t dw dq[15:0] out v oh v ol t whz t bw t lz t dh t a s t wp t wph hi g h-z hi g h-z
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 46 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 36: we#-controlled asynchronous write v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[19:0] adv# c e# lb#/ub# oe# we# wait dq[15:0] in v ih v il valid addre ss t w c t c ew t hz valid input t aw don ? t c are t wr t dw dq[15:0] out v oh v ol t whz t bw t c w t lz t wp t dh t ow t a s t wph hi g h-z hi g h-z hi g h-z
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 47 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 37: asynchronous write using adv# v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[19:0] adv# c e# lb#/ub# oe# we# wait dq[15:0] in v ih v il valid addre ss hi g h-z hi g h-z t c ew t hz valid input t v s don ? t c are t c w t dw dq[15:0] out v oh v ol t whz t bw t lz t wp t dh t ow t a s t wph t a s t vph t avh t av s t vp t aw hi g h-z
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 48 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 38: burst write operation note: non-default bcr settings for burst write operation: latency code two (three clocks); wait active low; wait asserted. a[19:0] v ih v il adv# v ih v il c e# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol c lk v ih v il v ih v il t c lk t kp t s p t hd t cs p t c em d[3] d[2] d[1] d[0] valid addre ss t hd t s p t hd t s p t hd t s p hi g h-z hi g h-z lb#/ub# v ih v il t s p t hd t hd don ? t c are write burst i d entifie d (we# = low) t c bph t khtl t hz t c ew t kp t khkl
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 49 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 39: continuous burst write showing an output delay with bcr[8] = 0 for end-of-row condition notes: 1. non-default bcr settings for continuous bu rst write, bcr[8] = 0; wait active low; wait asserted during delay. do not cross row boundaries with fixed latency. 2. ce# must not remain low longer than t cem. 3. wait asserts for anywhere from lc to 2lc cycles. lc = latency code (bcr[13:11]). 4. taking ce# high or adv# low on the start-of -row cycle will abort the burst and not write the start-of-row data. devices from different cellularram vendors can assert wait so that the start-of-row data is input just before (as show n), or just after wait asserts. this differ- ence in behavior will not be noticed by contro llers that monitor wait, or that use wait to abort on the start-of-row input cycle. a[19:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v ih v il t khtl t khtl t clk t sp t hd valid input valid input start of row (a[6:0] = 00h) (note 4) end of row (a[6:0] = 7fh) note 3 note 4 valid input valid input don?t care v ih v il lb#/ub#
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 50 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 40: burst write followed by burst read notes: 1. non-default bcr settings for burst write followed by burst read: latency code two (three clocks); wait active low; wait asserted during delay. 2. when configured for synchronous mode (bcr [15] = 0), a refresh opportunity must be pro- vided every t cem. a refresh opportunity is satisfied by either of the following two condi- tions: a) clocked ce# hi gh, or b) ce# high for greater than 15ns. note that the cellularram workgroup 1.0 specification requires ce# to be clocked high to terminate the burst. 3. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. a[19:0] v ih v il adv# v ih v il c e# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] in/out v oh v ol c lk v ih v il v ih v il t c lk t s p t s p t hd t cs p d[3] d[2] d[1] d[0] valid addre ss t hd t s p t hd t s p t s p t hd valid addre ss t aba t cs p t ohz t koh t a c lk valid output valid output valid output valid output hi g h-z hi g h-z v oh v ol lb#/ub# v ih v il t hd t s p t hd t s p t hd t hd hi g h-z undefined don ? t c are t boe t c bph 2 hi g h-z t s p t hd
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 51 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 41: asynchronous wr ite followed by burst read notes: 1. non-default bcr settings for asynchrono us write followed by burst read: latency code two (three clocks); wait active low; wait asserted during delay. 2. when configured for synchronous mode (bcr [15] = 0), a refresh opportunity must be pro- vided every t cem. a refresh opportunity is satisfied by either of the following two condi- tions: a) clocked ce# hi gh, or b) ce# high for greater than 15ns. note that the cellularram workgroup 1.0 specification requires ce# to be clocked high to terminate the burst. 3. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. t c lk t s p t hd t s p t hd valid addre ss t ohz t koh t a c lk hi g h-z hi g h-z valid addre ss valid addre ss t av s t avh t aw t wr t vp t v s t c ka a[19:0] v ih v il adv# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] in/out v oh v ol c lk v ih v il v ih v il v oh v ol c e# v ih v il lb#/ub# v ih v il t c w t wph t a s t a s t wp t w c t dh t dw data data hi g h-z t c v s t hd t s p t c ew t s p t hd t cs p t w c t w c t bw t whz valid output valid output valid output valid output don ? t c are undefined t aba t boe t c bph 2 t vph
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 52 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 42: asynchronous write fo llowed by burst read ? adv# low notes: 1. non-default bcr settings for asynchrono us write followed by burst read: latency code two (three clocks); wait active low; wait asserted during delay. 2. when configured for synchronous mode (bcr [15] = 0), a refresh opportunity must be pro- vided every t cem. a refresh opportunity is satisfied by either of these conditions: a) clocked ce# high, or b) ce# high for greater than 15ns. note that the cellularram workgroup 1.0 specification requires ce# to be clocked high to terminate the burst. 3. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. valid addre ss valid addre ss a[19:0] v ih v il adv# v ih v il oe# we# wait dq[15:0] in/out v oh v ol v ih v il v oh v ol c e# lb#/ub# v ih v il v ih v il v ih v il v ih v il t c w t wph t wp t w c t dh t dw t hz data t hz hi g h-z valid addre ss t aa t bhz t c ph 1 t c o valid output hi g h-z t oe t olz t lz t blz t ohz t hz t aw t wr t bw don ? t c are undefined data
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 53 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 43: burst read followed by asynchronous write (we#-controlled) notes: 1. when configured for synchronous mode (b cr[15] = 0), a refresh opportunity must be pro- vided every t cem. a refresh opportunity is satisfied by either of the following two condi- tions: a) clocked ce# high, or b) ce# high for greater than 15ns. note that cellularram workgroup specification 1.0 requires ce# to be clocked high to terminate the burst. a[19:0] v ih v il adv# v ih v il c e# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol c lk v ih v il v oh v ol t s p t c lk t a c lk t c ew t hd t aba t aw t c w t wr valid output valid addre ss hi g h-z t koh t dw t ohz t s p t hd lb#/ub# v ih v il t cs p hi g h-z t olz t hd t wp t wph t a s t dh t hz t hd t bw t s p t hz t hd t s p read burst i d entifie d (we# = hi g h) t w c t khtl t boe valid addre ss valid input hi g h-z t c ew t c bph 1 don ? t c are undefined
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 54 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 44: burst read followed by asynchronous write using adv# notes: 1. when configured for synchronous mode (b cr[15] = 0), a refresh opportunity must be pro- vided every t cem. a refresh opportunity is satisfied by either of the following two condi- tions: a) clocked ce# high, or b) ce# high for greater than 15ns. note that cellularram workgroup specification 1.0 requires ce# to be clocked high to terminate the burst. a[19:0] v ih v il adv# v ih v il c e# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol c lk v ih v il v oh v ol t s p t c lk t c ew t hd t aba t vph t v s t av s t avh t aw t c w valid output valid addre ss hi g h-z t koh t dw t ohz t s p t hd t vp lb#/ub# v ih v il t cs p hi g h-z t olz t hd t wp t wph t a s t dh t hd t bw t s p t hz t hd t s p undefined don ? t c are read burst i d entifie d (we# = hi g h) t khtl valid addre ss valid input hi g h-z t c ew t hz t c bph 1 t a c lk t boe t a s
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 55 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 45: asynchronous write follow ed by asynchronous read ? adv# low notes: 1. when configured for synchronous mode (b cr[15] = 0), ce# must remain high for at least 5ns ( t cph) to schedule the ap propriate internal refresh operation. otherwise, t cph is only required after ce#-controlled writes. valid addre ss valid addre ss a[19:0] v ih v il adv# v ih v il oe# we# wait dq[15:0] in/out v oh v ol v ih v il v oh v ol c e# lb#/ub# v ih v il v ih v il v ih v il v ih v il t c w t wph t wp t w c t dh t dw t hz data t hz hi g h-z valid addre ss t aa t bhz t c ph 1 t c o valid output hi g h-z t oe t olz t lz t blz t ohz t hz t aw t wr t bw don ? t c are undefined data
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 56 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 46: asynchronous write followed by asynchronous read notes: 1. when configured for synchronous mode (b cr[15] = 0), ce# must remain high for at least 5ns ( t cph) to schedule the ap propriate internal refresh operation. otherwise, t cph is only required after ce#-controlled writes. valid addre ss valid addre ss t av s t avh t vph t vp t v s a[19:0] v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il adv# oe# we# wait dq[15:0] in/out v oh v ol v ih v il v oh v ol c e# lb#/ub# t vp t avh t c w t wph t a s t wp t w c t dh t dw data data hi g h-z valid addre ss t aa t bhz t aadv t c ph 1 t c o valid output hi g h-z t c v s t olz t lz t a s t blz t ohz t hz t aw t wr t bw undefined don ? t c are t oe t av s t c v s
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. cellularram is a tra demark of micron technology, inc. inside the u.s. and a tra demark of infineon technol ogies outside the u.s. all other trademarks are the prop- erty of their respective owne rs. this data sheet contains minimum and maxi mum limits specified over the complete power supply and temperature range for production d evices. although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory package dimensions pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 57 ?2005 micron technology, inc. all rights reserved. package dimensions figure 47: 54-ball vfbga notes: 1. all dimensions in millimete rs; max/min, or typical, as noted. 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. the mt45w1mw16bdgb uses ?green? packaging. ball a1 id 0.70 0.05 seating plane 0.10 a a 1.00 max ball a6 ball a1 ball a1 id 0.75 typ 0.75 typ 1.875 3.75 6.00 0.10 3.00 0.05 dimensions apply to solder balls post reflow. pre-reflow ball diameter is 0.35 on a 0.30 smd ball pad. 54x ?0.37 solder ball material: 96.5% sn, 3% ag, 0.5% cu mold compound: epoxy novolac substrate material: plastic laminate 6.00 3.00 4.00 0.05 8.00 0.10
pdf: 09005aef81cb58ed/source: 09005aef81c7a667 micron technology, inc., reserves the right to change products or specifications without notice. 16mb_burst_cr1_0_p23z_2.fm - rev. f 12/ 06 en 58 ?2005 micron technology, inc. all rights reserved. 16mb: 1 meg x 16 async/page/burst cellularram 1.0 memory revision history revision history rev. f, production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/06 ?updated rev. letter to f rev. f, production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .06/06 ? changed the title of figure 10 to ?wired-or wait configuration? ? updated wording in the third paragraph of ?wait operation? on page 15 to the following: ?during a burst cycle, ce# must remain asserted until the first data is valid. bringing ce# high during this initial latency may cause data corruption.? ?changed wait from ? t cw? to ? t cew? in figure 14 ? changed min/max columns fr om ?-701? and ?-708,? to ?104 mhz? and ?80 mhz? in tabl e 5 ? changed ?output enable to low-z output? min value from 5 to 3 in table 12 ? changed min/max columns from ?-70? to ?70ns? in table 12 ? removed ?clk to dq high-z output? and ?clk to low-z output? rows from tabl e 13 ? changed ?output enable to low-z output? min value from 5 to 3 in table 13 ? changed min/max columns fr om ?-701? and ?-708,? to ?104 mhz? and ?80 mhz? in tabl e 13 ? changed min/max columns from ?-70? to ?70ns? in table 14 ? changed min/max columns fr om ?-701? and ?-708,? to ?104 mhz? and ?80 mhz? in tabl e 15 ? changed min/max columns from ?-70? to ?70ns? in table 16 ? removed twhz lines and arrows in figure 42 ? removed twhz lines and arrows in figure 45 ? removed twhz lines and arrows in figure 46 rev. e, production. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .02/06 rev. d, preliminary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .01/06 ?changed v ih and v il to v oh and v ol in figure 27, 28, 29, 34, 35, 36, 37 ? updated continuous burst read and standb y specifications in ?features? section ? updated document designator to preliminary ? deleted tables 17?43. rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12/05 ? deleted ?4-word burst read operation (with lb#/ub#)? timing diagram ? changed file name to new standard: p23z16_b_cr1-0 to 16mb_burst_cr1_0_p23z rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10/05 ? fixed exceptions to template (pri marily minor formatting on page 1) ? page 1, figure 1: changed e3 ball color to white ? page 1: changed multiple ?-? to ??? for negative numbers (per style) ? eliminated holdover references to dual parts (pgs. 10 and 30) ? updated to state that ?clk must be held static low or high ? during async read and write (pgs. 7, 10, 11, 14) ? updated note 4 in table 8 to eliminate reference to dual part (was ?bcr[5:4] = 00b?) rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .08/05 ? initial release with ?advance? designation.

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